Samsung Electronics, the global leader in memory chip manufacturing, is gearing up to introduce a three-dimensional (3D) chip packaging technology in the coming year. By greatly reducing chip size, SAINT (Samsung Advanced Interconnection Technology) aims to address the escalating demand for more efficient AI semiconductors and challenge the industry status quo, which TSMC dominates.
This approach discards the traditional 2.5D horizontal chip placement and involves vertical stacking, enabling the creation of much smaller-sized chips. With chips stacked vertically, data processing accelerates between semiconductors, substantially boosting power efficiency. Following successful validation tests, Samsung will launch commercial services featuring the SAINT technologies next year.
The three distinct types of SAINT technologies, SAINT S, SAINT D, and SAINT L, accommodate various chip configurations. The demand for such advanced AI semiconductors is predicted to surge, with the market expected to reach a staggering $78 billion by 2028.
SAINT S vertically stacks SRAM memory chips and the CPU, SAINT D involves the vertical packaging of processors like the CPU and GPU alongside DRAM memory, while SAINT L stacks application processors (APs).
Among the SAINT technologies, SAINT S, the inaugural iteration, has successfully passed validation tests, featuring the vertical stacking of SRAM memory chips on top of a processor, such as a central processing unit (CPU).
Samsung plans to conduct further tests with clients before launching commercial services next year. Additionally, SAINT D, set for technology verification in the upcoming year, entails the vertical placement of DRAM for data storage on processors like CPU and graphics processing unit (GPU). Another upcoming innovation, SAINT-L, aims to position application processors (APs) above and below the stack.
In semiconductor manufacturing, packaging stands out as a key final step. This process involves encasing chips in a protective covering to shield against corrosion while furnishing an interface for combining and connecting pre-manufactured chips.
Key players in the semiconductor industry, including TSMC, Samsung, and Intel Corp., are engaged in intense competition for advanced packaging techniques.
The pursuit of advanced packaging is a response to the challenges posed by ultra-fine processing technology, which hinders the downsizing of individual chips. By adeptly arranging and connecting manufactured chips semiconductor companies, Samsung aims to leverage packaging as a critical process to enhance performance without the need for nanometer shrinking, a technically intricate and time-consuming process.
The global market keenly awaits the unfolding developments in this technological evolution. 3D packaging is anticipated to carve a niche within the market, constituting approximately a quarter and amounting to $15 billion. Currently, the mainstream packaging approach involves the 2.5D format, aimed at minimizing data bottlenecks by placing chips in close proximity.
In response to these trends, TSMC, a key player in the semiconductor industry, is making $90 billion investments in its 3D inter-chip stacking technology, known as SoIC.
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